1. Field of the Invention
The present invention relates to a clock and data recovery circuit and a communications apparatus including the clock and data recovery circuit.
2. Description of the Related Art
Universal Serial Bus (USB) is a standard for connecting a personal computer to a peripheral device. USB 2.0 is a high-speed USB standard for serial communications with a maximum transfer rate of 480 Mbps. With its great improvement in transfer rate and reduced system load, the USB 2.0 has come into widespread use.
In serial communications, data is transmitted and received over a pair of data lines D+ and D− using small-amplitude differential signals without a clock. Generally, a receiver extracts a clock from the received data, which is then sampled with the extracted clock to obtain the data. A circuit that extracts a clock and data from received data is referred to as a clock and data recovery circuit, generally referred to as a CDR circuit.
The CDR circuit used in a high-speed serial interface is a technology to regenerate a clock based on a transition in received data. The CDR circuit generally uses an analog PLL (Phase Locked Loop) to extract a clock synchronous to an edge of the received data and sample the received data with the clock.
Since digital circuit blocks are integrated onto a LSI (Large Scale Integrated) circuit using a fine fabrication process, high-speed operation becomes possible even for a rapid increase in serial transfer rate such as that of USB 2.0. However, it is not easy to apply the fine fabrication process to an analog circuit block with a size similar to that of the digital circuit block. Consequently, if the LSI circuit includes a conventional analog PLL, the cost of the circuit is relatively high.
For connection between circuit boards or between LSI circuits in an apparatus, high-speed serial interfaces such as PCI Express have been recently used. However, an increase in the number of channels results in not only cost penalties bus also noise interference when each channel is provided with an analog PLL.
There is a high-speed serial interface circuit that uses a digital PLL instead of an analog PLL. However, the digital PLL needs an operation clock with a frequency of at least three times greater than a frequency of the extracted clock. Accordingly, it is difficult to employ the digital PLL in recent high-speed serial communication systems in view of resulting increases in cost and power consumption.
Whether analog or digital, the PLL samples received data with an extracted clock to regenerate data. Since the clock extracted by the PLL is asynchronous to the clock at the receiver, the synchronous design technique mostly used in digital LSI design is unavailable, thus increasing development time including design verification.
There are a number of CDR circuits that regenerate a clock and data without using an analog circuit. However, such a CDR circuit needs a large circuit block that samples data with multi-phase clocks. Since the multi-phase clocks with different delays need to be input (re-synchronized) together, both layout and simulation required to study the behavior of the circuit are difficult to achieve even with digital circuits. In particular, the difficulty increases dramatically with higher speed operation.
In a serial transfer operation, the frequency of a serial clock at a transmission side cannot be equal to the frequency of a serial clock at a receiving side. To absorb the frequency difference therebetween, a buffer (generally referred to as an elastic buffer) is needed. The elastic buffer includes a FIFO (First In First Out) register in which data is written synchronously to the clock extracted from received data (i.e., the serial clock at the transmission side) and data is read synchronously to the serial clock at the receiving side. Since the writing and the reading operations are not synchronous, the timing of these operations needs to be controlled by an asynchronous circuit, which complicates both the circuitry and the simulations required to study the behavior of the circuit. This problem may be solved by an elastic buffer that operates cooperatively with the CDR circuit with one type of clock. However, such an elastic buffer has not yet been disclosed.
To solve the problems described above, another approach has been proposed in which the data is sampled with multi-phase clocks and a clock pattern is determined based on the pattern of the sampling data. However, it is difficult to qualitatively determine each parameter in the CDR circuit. Therefore, it may be preferable that, in addition to regenerating a clock based on a transition in received data, the CDR circuit set a period of time to respond to the transition (a loop gain of a PLL) and a phase difference between the received data and the clock (a steady-state error of a PLL) as parameters. However, such setting is difficult to achieve with conventional techniques.